The present invention relates to a flattening method and a flattening apparatus for a semiconductor device for flattening, by a chemical-mechanical polishing process, portions requiring flatness on uneven surfaces of elements constituting a semiconductor device, such as a metal wiring, polysilicon film, epitaxial growth film, resistance film, metal plug, silicon nitride film and inter-layer insulating film. In particular, the invention relates to a flattening method and a flattening apparatus for a semiconductor device for controlling a polishing rate by forming a surface layer or recreating a surface shape of a polishing cloth, so that the polishing rate on a whole wafer surface is kept uniform.
Recently, for producing multi-layer and high density IC and LSI, flattening of a wiring layer and an inter-layer insulating layer has been required. The word "flatness" means, for example, that a surface of the inter-layer insulating film must be formed to be a straight line parallel to the surface of a wafer and a support plate in a micro view, and to be curved so as to have the same wave as those of the surface of the wafer and the support plate in a macro view.
The reason why the flatness is required for the multi-layer IC and LSI is described hereunder. For example, in case a multi-layer IC is produced, as shown in FIGS. 22(A) through 22(E), first, a flat semiconductor support plate 1, i.e. a silicon wafer, is provided with lower layer wirings 2a, 2b and 2c of the same height. In the drawing, only electrodes of upper portions of the wirings are shown.
An inter-layer insulating film 3 is formed on the lower layer wirings 2a, 2b and 2c, then contact holes 3a, 3b and 3c are formed, and an upper layer wiring 4 is further formed to contact the lower wirings 2a, 2b and 2c.
At this time, if a thickness of the inter-layer insulating film 3 on the lower layer wirings 2a, 2b and 2c is not uniform, when the contact holes 3a, 3b and 3c are formed, the contact holes may not reach the lower layer wirings 2a, 2b and 2c as shown in FIG. 22(E), or the wirings may be etched, which results in cutting the wirings. Further, in case a photolithography is applied, a line width tends to be thin according to a design rule, and a wave length of ultraviolet rays becomes short, so that a focus depth becomes shallow. Therefore, in case level difference and unevenness are great, an image may not be formed. Therefore, the flatness is required for fine wirings.
Incidentally, in a semiconductor device including a logic circuit and a memory circuit, especially such as ASIC, a conventional flattening method of an inter-layer insulating film in combination of a reflow method and an etching method by subjecting to a high temperature treatment results in a high cost due to increased number of steps. This problem arises when an element includes a high density portion and a coarse density portion of a wiring, irrespective of a logic circuit or memory circuit.
As shown in FIGS. 21(A), 21(B) and 21(C), even if a surface of an inter-layer insulating film 3 is flattened by a reflow method in FIG. 21(B) and an etching method in FIG. 21(C) to obtain a flattened surface 6, when intervals among wirings 5a, 5b and 5c are over 200 .mu.m, it is technically difficult to flatten the surface of the inter-layer insulating film. Therefore, in view of simplifying the process steps and lowering the cost, a chemical-mechanical polishing technique which has been used in a mirror surface polishing of a semiconductor substrate has been adopted to obtain a flattened surface of the inter-layer insulating film.
The chemical-mechanical polishing technique is a technique where, as shown in FIGS. 20(A) and 20 (B), uneven portions of an inter-layer insulating film 3 are polished to be flattened on the basis of a wafer surface 1a.
In the chemical-mechanical polishing technique, in case a fine area in a tip is polished, the area is to be polished in a straight line as shown in FIG. 20(A). However, when considering a wafer 1 as a whole, it is required that the inter-layer insulating film 3 is polished to accord with the unevenness of the wafer 1. More specifically, as shown by a phantom line in FIG. 20(B), the inter-layer insulating film 3 is required to be polished to accord with the unevenness (wave) of the wafer 1, which is flattened from a micro view and uniformity from a macro view.
The polishing requirements appear to be inconsistent, but it is possible to attain the requirements with improvements of a structure of a polishing apparatus and a polishing method. This improvement allows all tips a-d on the wafer 1 to be formed uniformly as shown in FIG. 19. Therefore, if the inter-layer insulating film can be polished in an equal quantity, it is beside the question whether the polishing is carried out based on a back surface or a front surface of the wafer 1.
The following flattening techniques employing the chemical-mechanical polishing process have been known as prior art.
A flattening technique is disclosed in, for example, Japanese Patent Publication (KOKOKU) No. 5-30052.
That is, "a method for producing a semiconductor device characterized in that an inter-layer insulating film for insulating between a wiring provided on the semiconductor device and a wiring provided on an upper layer thereof is interposed, and then chemical-mechanical polishing is applied thereon to thereby flatten a surface of the inter-layer insulating film" is disclosed.
The Japanese Patent Publication only discloses that the chemical-mechanical polishing apparatus is capable of polishing a plurality of wafers at a time by using the conventional polishing apparatus for polishing a mirror surface of a silicon substrate plate. However, it does not disclose any specific method and apparatus.
Further, a polishing apparatus to be used in flattening is disclosed in Japanese Patent Publication (KOHYO TOKKYO) No. 5-505769.
More specifically, "in a polishing apparatus for polishing a surface of an object to be polished including flat laying surfaces in a macro view and at least a pair of elements connected to the respective laying surfaces with a substantially equal distance away from the respective laying surfaces and disposed with a distance less than 500 .mu.m therefrom, the surface to be polished being an upper surface of a coating layer covering the elements and the laying surfaces and being flat in a macro view and uneven in a micro view so that the elements are exposed and the surface to be polished is flattened in a micro view by polishing, said polishing apparatus comprises the following (a), (b) and (c):
(a) polishing pad means including the following (A), (B), (C) and (D);
(A) a substrate; (B) a first layer formed of an elastic material having a distortion constant higher than 6.mu./psi when received a predetermined pressure over 4 psi, and affixed to one side of the substrate with an opposite side thereof as an outer surface; (C) a second layer formed of an elastic material having a distortion constant smaller than that of the first layer when received the predetermined pressure as mentioned in (B) and contacting at least the outer surface mentioned in (B) to thereby polish the opposite side thereof; and (D) a slurry liquid for polishing to be supplied to the second polishing surface as an abrasive,
(b) holding means for holding an object to be polished so that a surface to be polished faces a polishing surface, and
(c) a moving device for moving at least one of the polishing pad means and the holding means to the other side thereof so that the slurry liquid for polishing and the polishing surface are brought into contact with the surface to be polished to thereby polish the surface to be polished."
However, the prior art only discloses a mode of a composite polishing cloth, and does not disclose a technique for forming a surface layer of a polishing cloth required in case polishing is carried out by using the polishing cloth, or a technique for recreating a surface shape of the polishing cloth.
At present, as shown in FIG. 18, when an inter-layer insulating film 8 for insulating wirings 7 on a wafer 1 of a semiconductor device is flattened by a chemical-mechanical polishing method, a two-layer polishing cloth including an upper layer polishing cloth 9 formed of a hard synthetic resin and a lower layer polishing cloth 10 formed of a soft unwoven cloth and affixed to a support plate 11, is generally used. Incidentally, numeral 12 represents a template for a chuck for holding the silicon wafer 1, and 13 represents a backing pad.
The reason why the polishing cloth is formed of two layers is that the polishing cloth is required to have a softness to follow a wave of the silicon wafer 1 and a hardness to smooth a surface of an object to be polished. On the contrary, a suede type polishing cloth which has been generally used for polishing a mirror surface of a silicon base is very soft so that sags are created on a peripheral portion of the wafer.
However, since an area on the wafer is used as wide as possible in order to increase a yield rate, an "exclusion" is required to be as little as possible. The "exclusion" means how many millimeters are excluded from an outer periphery. Therefore, it is naturally undesirable that the sags become large on the outer peripheral portion. Thus, the suede type polishing cloth is not suitable for flattening. In case an inter-layer insulating film is polished, as a quantity to be removed is increased, the sags become large.
Also, the conventional unwoven type polishing cloth is very soft, so that the unwoven type cloth does not polish a surface to be flat and is easily damaged. Therefore, in case a semiconductor device is polished by using the chemical-mechanical polishing method, it is necessary that the polishing cloth has a two layer structure including the lower soft layer and the upper hard layer.
Further, as techniques for forming a surface layer of a polishing cloth and for recreating a surface shape of a polishing cloth, Japanese Utility Model Publication (KOKAI) No. 62-95865, Japanese Patent Publication (KOKAI) No. 4-343658 and Japanese Patent Publication (KOKAI) No. 5-177534 are mentioned.
In Publication No. 62-95865, a technique for removing polishing scraps from a polishing cloth is disclosed, and does not concern fluffing on a surface of a polishing cloth, i.e. formation of a surface layer of a polishing cloth. The technique does not disclose techniques for forming a surface layer of a polishing cloth and for recreating a surface shape of a polishing cloth according to the present invention.
Publication No. 4-343658 discloses that in case chaps, such as fluffs and waves, are created on a surface of a polishing cloth, the polishing accuracy is decreased. Also, since outer peripheral portions of an area where a wafer passes on the polishing cloth are inclined, the wafer can not be polished flat. Therefore, the chaps on the polishing cloth are corrected.
However, as described later, contrary to the concept of Publication No. 4-343658, in the present invention, the fluffs, i.e., a surface layer is intended to be formed on a polishing cloth. Also, Publication No. 4-343658 discloses that when the wafer passing portion is inclined, the wafer can not be polished flat. However, in the present invention, the surface shape of the polishing cloth is intended to be recreated so that the area where a wafer passes is positively kept in an inclined shape, convex shape, concave shape or flat shape.
Further, Publication No. 5-177534 discloses that after polishing in a high pressure area, it is desirable to correct changes, such as mesh-clogging, with passage of time of the polishing cloth in the high pressure area by carrying out grinding with a diamond dresser. However, there are not shown a technique of the present invention where a surface of a polishing cloth is fluffed to form a surface layer of the polishing cloth, and a technique where an area of the polishing cloth including a portion which slidingly contacts a wafer is positively held in the same shape, such as a convex shape, concave shape or flat shape, as that of a backing pad on a wafer holding side. In other words, recreation of the surface shape of the polishing cloth is not disclosed therein.
In "Electronics Materials" published on March, 1994, chemical mechanical polishing for inter-layer is disclosed, wherein the inter-layer is polished by a grinding pad formed of hard resin portions supported by soft elastic materials. Also, a grinding material in a slurry form is used for polishing. A support for a material to be ground is rotated on its own axis while being rotated around a different axis.